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pret group is for the discussion of Precision Timed (PRET) Machines, which are introduced in:
"The Case for the Precision Timed (PRET) Machine,"
Stephen Edwards and Edward A. Lee, EECS Department,
University of California, Berkeley, Technical Report No. UCB/EECS-2006-149, November 17, 2006
We argue that at least for embedded software applications, computer architecture, software, and networking have gone too far down the path of emphasizing average case performance over timing predictability. In architecture, techniques such as multi-level caches and deep pipelines with dynamic dispatch and speculative execution make worst-case execution times (WCET) highly dependent on both implementation details of the processor and on the context in which the software is executed. Yet virtually all real-time programming methodologies depend on WCET. When timing properties are important in the software and when concurrent execution is affected by timing, the result is brittle designs. In this paper, we argue for precision timed (PRET) machines, which deliver high performance, but not at the expense of timing predictability. We summarize a number of research approaches that can be used to create PRET machines, and discuss how the software, operating system, and networking abstractions built above the machine architecture will have to change.
PRET Receives Funding from the NSF
On June 30, 2007, Columbia University News reports:
Prof. Steve Edwards, along with Prof. Edward Lee at UC Berkeley, has been awarded a three-year National Science Foundation grant titled "PRET: Precision Timed Architectures".
This project proposes to reintroduce timing predictability as a first-class property of embedded processor architectures. To fully exploit such timing predictability, however, would require a significant redesign of much of computing technology, including operating systems, programming languages, compilers, and networks.
Obviously, a three-year NSF project cannot address the full breadth of the problem. We propose, therefore, to tackle the problem from the hardware design perspective. Our approach will be to develop precision timed (PRET) machines as soft cores on FPGAs, and to show that using such machines software components can be integrated with what would traditionally have been purely hardware designs. We expect that this will first greatly improve the expressiveness and usability of FPGA-based design flows, and second will provide a starting point for a decades-long revolution that will once again make timing
predictability an essential feature of processors.