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System-level Synthesis of Dataflow Applications for FPGA-based Distributed Platforms
Hugo Andrade, Kaushik Ravindran, Alejandro Asenjo, Casey Weltzin

Citation
Hugo Andrade, Kaushik Ravindran, Alejandro Asenjo, Casey Weltzin. "System-level Synthesis of Dataflow Applications for FPGA-based Distributed Platforms". Talk or presentation, 7, November, 2013; Presented at the 10th Biennial Ptolemy Miniconference, Berkeley.

Abstract
With the increasing popularity of FPGAs (due to their competitive and deployable performance and price), system-level synthesis of applications onto FPGA-based platforms is a key focus area for system-design tool and research communities. In particular, developing efficient and effective support for implementing advanced dataflow applications (such as next-generation communication systems, complex cyber-physical systems, or high performance scientific computations) by domain experts (with little or no knowledge of FPGA hardware and/or integration of I/O) is an important problem. In this talk we study the relevance of input language and model of computation in capturing user intent and their roles in increasing productivity for system designers, and summarize state-of-the-art techniques for implementing dataflow applications on FPGA-based distributed platforms. The presentation will focus on three topics: - (a) synthesis of domain-centric algorithms (targeted for a single FPGA) while optimizing for constraints like performance and area using directives (also called high-level synthesis or HLS); - (b) application design using domain specific models of computation (which formally captures design intent), and associated analysis of key properties and subsequent implementation on a single FPGA; and - (c) synthesis of system level applications for multi-FPGA platforms; the last step integrates techniques for (a) and (b), and additionally solves mapping and synchronization of distributed computation and communication. We conclude by discussing a more general problem of implementing system-level applications over heterogeneous multi-target platforms that include traditional instruction processors, FPGAs, GPUs, specialized processors, and accelerators. Along the way, we also highlight related research efforts at National Instruments R&D in these areas.

Electronic downloads

Citation formats  
  • HTML
    Hugo Andrade, Kaushik Ravindran, Alejandro Asenjo, Casey
    Weltzin. <a
    href="http://chess.eecs.berkeley.edu/pubs/1025.html"><i>System-level
    Synthesis of Dataflow Applications for FPGA-based
    Distributed Platforms</i></a>, Talk or
    presentation,  7, November, 2013; Presented at the <a
    href="http://ptolemy.org/conferences/13" >10th
    Biennial Ptolemy Miniconference</a>, Berkeley.
  • Plain text
    Hugo Andrade, Kaushik Ravindran, Alejandro Asenjo, Casey
    Weltzin. "System-level Synthesis of Dataflow
    Applications for FPGA-based Distributed Platforms".
    Talk or presentation,  7, November, 2013; Presented at the
    <a href="http://ptolemy.org/conferences/13"
    >10th Biennial Ptolemy Miniconference</a>, Berkeley.
  • BibTeX
    @presentation{AndradeRavindranAsenjoWeltzin13_SystemlevelSynthesisOfDataflowApplicationsForFPGAbased,
        author = {Hugo Andrade and Kaushik Ravindran and Alejandro
                  Asenjo and Casey Weltzin},
        title = {System-level Synthesis of Dataflow Applications
                  for FPGA-based Distributed Platforms},
        day = {7},
        month = {November},
        year = {2013},
        note = {Presented at the <a
                  href="http://ptolemy.org/conferences/13" >10th
                  Biennial Ptolemy Miniconference</a>, Berkeley.},
        abstract = {With the increasing popularity of FPGAs (due to
                  their competitive and deployable performance and
                  price), system-level synthesis of applications
                  onto FPGA-based platforms is a key focus area for
                  system-design tool and research communities. In
                  particular, developing efficient and effective
                  support for implementing advanced dataflow
                  applications (such as next-generation
                  communication systems, complex cyber-physical
                  systems, or high performance scientific
                  computations) by domain experts (with little or no
                  knowledge of FPGA hardware and/or integration of
                  I/O) is an important problem. In this talk we
                  study the relevance of input language and model of
                  computation in capturing user intent and their
                  roles in increasing productivity for system
                  designers, and summarize state-of-the-art
                  techniques for implementing dataflow applications
                  on FPGA-based distributed platforms. The
                  presentation will focus on three topics: - (a)
                  synthesis of domain-centric algorithms (targeted
                  for a single FPGA) while optimizing for
                  constraints like performance and area using
                  directives (also called high-level synthesis or
                  HLS); - (b) application design using domain
                  specific models of computation (which formally
                  captures design intent), and associated analysis
                  of key properties and subsequent implementation on
                  a single FPGA; and - (c) synthesis of system level
                  applications for multi-FPGA platforms; the last
                  step integrates techniques for (a) and (b), and
                  additionally solves mapping and synchronization of
                  distributed computation and communication. We
                  conclude by discussing a more general problem of
                  implementing system-level applications over
                  heterogeneous multi-target platforms that include
                  traditional instruction processors, FPGAs, GPUs,
                  specialized processors, and accelerators. Along
                  the way, we also highlight related research
                  efforts at National Instruments R\&D in these
                  areas. },
        URL = {http://chess.eecs.berkeley.edu/pubs/1025.html}
    }
    

Posted by Barb Hoversten on 16 Nov 2013.
Groups: chess
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