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A Multi-Threaded Reactive Processor
Reinhard von Hanxleden, Xin Li, Marian Boldt

Citation
Reinhard von Hanxleden, Xin Li, Marian Boldt. "A Multi-Threaded Reactive Processor". Talk or presentation, 18, September, 2007.

Abstract
Many embedded systems belong to the class of reactive systems, which continuously react to inputs from the environment by generating corresponding outputs. The programming of reactive systems typically requires the use of non-standard control flow constructs, such as concurrency or exception handling. The synchronous language Esterel has been developed to express reactive control flow patterns in a concise manner, with a clear semantics that imposes deterministic program behavior under all circumstances. However, classical Esterel synthesis approaches suffer from the limitations of traditional processors, with their instruction set architectures geared towards the sequential von-Neumann execution model, or they are very inflexible if HW synthesis is involved.rnrn

Recently, another alternative for synthesizing Esterel has emerged, the reactive processing approach. This talk presents a multi-threaded reactive processor, the Kiel Esterel Processor (KEP). The KEP Instruction Set Architecture supports reactive control flow directly, and provides a very dense encoding; code size is typically an order of magnitude smaller than that of the MicroBlaze, a 32-bit COTS RISC processor core. The worst case reaction time is typically improved by 4x, and energy consumption is also typically reduced to a quarter. Apart from efficiency and determinism concerns, another advantage of reactive processors is that due to their comparatively simple structure (no caches, no pipelining) and their direct implementation of the synchronous model of computation it becomes feasible to precisely characterize their timing behavior.

Electronic downloads

Citation formats  
  • HTML
    Reinhard von Hanxleden, Xin Li, Marian Boldt. <a
    href="http://chess.eecs.berkeley.edu/pubs/352.html"
    ><i>A Multi-Threaded Reactive
    Processor</i></a>, Talk or presentation,  18,
    September, 2007.
  • Plain text
    Reinhard von Hanxleden, Xin Li, Marian Boldt. "A
    Multi-Threaded Reactive Processor". Talk or
    presentation,  18, September, 2007.
  • BibTeX
    @presentation{vonHanxledenLiBoldt07_MultiThreadedReactiveProcessor,
        author = {Reinhard von Hanxleden and Xin Li and Marian Boldt},
        title = {A Multi-Threaded Reactive Processor},
        day = {18},
        month = {September},
        year = {2007},
        abstract = {Many embedded systems belong to the class of
                  reactive systems, which continuously react to
                  inputs from the environment by generating
                  corresponding outputs. The programming of reactive
                  systems typically requires the use of non-standard
                  control flow constructs, such as concurrency or
                  exception handling. The synchronous language
                  Esterel has been developed to express reactive
                  control flow patterns in a concise manner, with a
                  clear semantics that imposes deterministic program
                  behavior under all circumstances. However,
                  classical Esterel synthesis approaches suffer from
                  the limitations of traditional processors, with
                  their instruction set architectures geared towards
                  the sequential von-Neumann execution model, or
                  they are very inflexible if HW synthesis is
                  involved.rnrn<p>Recently, another alternative for
                  synthesizing Esterel has emerged, the reactive
                  processing approach. This talk presents a
                  multi-threaded reactive processor, the Kiel
                  Esterel Processor (KEP). The KEP Instruction Set
                  Architecture supports reactive control flow
                  directly, and provides a very dense encoding; code
                  size is typically an order of magnitude smaller
                  than that of the MicroBlaze, a 32-bit COTS RISC
                  processor core. The worst case reaction time is
                  typically improved by 4x, and energy consumption
                  is also typically reduced to a quarter. Apart from
                  efficiency and determinism concerns, another
                  advantage of reactive processors is that due to
                  their comparatively simple structure (no caches,
                  no pipelining) and their direct implementation of
                  the synchronous model of computation it becomes
                  feasible to precisely characterize their timing
                  behavior. },
        URL = {http://chess.eecs.berkeley.edu/pubs/352.html}
    }
    

Posted by Douglas Densmore on 10 Oct 2007.
Groups: chess
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