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Single and Multi-CPU Performance Modeling for Embedded Systems (Dissertation Talk)
Trevor Meyerowitz

Citation
Trevor Meyerowitz. "Single and Multi-CPU Performance Modeling for Embedded Systems (Dissertation Talk)". Talk or presentation, 26, February, 2008.

Abstract
The combination of increasing design complexity, increasing concurrency, growing heterogeneity, and decreasing time to market windows has caused a crisis for embedded system developers. To deal with this, a growing number of microprocessors are being used to construct these systems, making software and its timing have become dominating factors. The use of higher level models for design space exploration and early software development is critical. Much progress has been made on increasing the speed of cycle-level simulators for microprocessors, but they may still be too slow for large scale systems and are too low-level for doing design space exploration. Another problem is that constructing such optimized simulators is in itself a significant task, and they generally aren’t that flexible. This work focuses on modeling the performance of software executing on embedded processors in the context of a heterogeneous multi-processor system on chip in a more flexible and scalable manner than current approaches. The thesis is that such systems needs to be modeled at a higher level of abstraction and, to ensure accuracy, the higher level must have a connection to lower-levels. First, we describe different levels of abstraction for modeling such systems and how their speed and accuracy relate. Next, the high-level modeling of oth individual processing elements and also a bus-based microprocessor system are presented. Finally, an approach for automatically annotating timing information obtained from a cycle-level model back to the original application source code is developed. The annotated source code can then be simulated without the underlying architecture and still maintain good timing accuracy. The above described methods are driven by execution traces produced by lower level models and were developed for ARM microprocessors and MuSIC, a heterogeneous multiprocessor for Software Defined Radio from Infineon. For running on the same code with the same data set the annotated source code executed between one to three orders of magnitude faster than equivalent cycle-level models, and had an average error magnitude of 4% (and a maximum of 20%).

Electronic downloads

Citation formats  
  • HTML
    Trevor Meyerowitz. <a
    href="http://chess.eecs.berkeley.edu/pubs/397.html"
    ><i>Single and Multi-CPU Performance Modeling for
    Embedded Systems (Dissertation Talk)</i></a>,
    Talk or presentation,  26, February, 2008.
  • Plain text
    Trevor Meyerowitz. "Single and Multi-CPU Performance
    Modeling for Embedded Systems (Dissertation Talk)".
    Talk or presentation,  26, February, 2008.
  • BibTeX
    @presentation{Meyerowitz08_SingleMultiCPUPerformanceModelingForEmbeddedSystems,
        author = {Trevor Meyerowitz},
        title = {Single and Multi-CPU Performance Modeling for
                  Embedded Systems (Dissertation Talk)},
        day = {26},
        month = {February},
        year = {2008},
        abstract = {The combination of increasing design complexity,
                  increasing concurrency, growing heterogeneity, and
                  decreasing time to market windows has caused a
                  crisis for embedded system developers. To deal
                  with this, a growing number of microprocessors are
                  being used to construct these systems, making
                  software and its timing have become dominating
                  factors. The use of higher level models for design
                  space exploration and early software development
                  is critical. Much progress has been made on
                  increasing the speed of cycle-level simulators for
                  microprocessors, but they may still be too slow
                  for large scale systems and are too low-level for
                  doing design space exploration. Another problem is
                  that constructing such optimized simulators is in
                  itself a significant task, and they generally
                  aren’t that flexible. This work focuses on
                  modeling the performance of software executing on
                  embedded processors in the context of a
                  heterogeneous multi-processor system on chip in a
                  more flexible and scalable manner than current
                  approaches. The thesis is that such systems needs
                  to be modeled at a higher level of abstraction
                  and, to ensure accuracy, the higher level must
                  have a connection to lower-levels. First, we
                  describe different levels of abstraction for
                  modeling such systems and how their speed and
                  accuracy relate. Next, the high-level modeling of
                  oth individual processing elements and also a
                  bus-based microprocessor system are presented.
                  Finally, an approach for automatically annotating
                  timing information obtained from a cycle-level
                  model back to the original application source code
                  is developed. The annotated source code can then
                  be simulated without the underlying architecture
                  and still maintain good timing accuracy. The above
                  described methods are driven by execution traces
                  produced by lower level models and were developed
                  for ARM microprocessors and MuSIC, a heterogeneous
                  multiprocessor for Software Defined Radio from
                  Infineon. For running on the same code with the
                  same data set the annotated source code executed
                  between one to three orders of magnitude faster
                  than equivalent cycle-level models, and had an
                  average error magnitude of 4% (and a maximum of
                  20%). },
        URL = {http://chess.eecs.berkeley.edu/pubs/397.html}
    }
    

Posted by Trevor Meyerowitz on 27 Feb 2008.
Groups: chess chesslocal
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