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Predictable Programming on a Precision Timed Architecture
Ben Lickly, Isaac Liu, Sungjun Kim, Hiren Patel, Stephen A. Edwards, Edward A. Lee

Citation
Ben Lickly, Isaac Liu, Sungjun Kim, Hiren Patel, Stephen A. Edwards, Edward A. Lee. "Predictable Programming on a Precision Timed Architecture". Proceedings of International Conference on Compilers, Architecture, and Synthesis from Embedded Systems (CASES), Atlanta, Georgia, Erik R. Altman (ed.), ACM, 137-146, 19, October, 2008; Published version available at ACM Portal.

Abstract
In a hard real-time embedded system, the time at which a result is computed is as important as the result itself. Modern processors go to extreme lengths to ensure their function is predictable, but have abandoned predictable timing in favor of average-case performance. Real-time operating systems provide timing-aware scheduling policies, but without precise worst-case execution time bounds they cannot provide guarantees.
We describe an alternative in this paper: a SPARC-based processor with predictable timing and instruction-set extensions that provide precise timing control. Its pipeline executes multiple, independent hardware threads to avoid costly, unpredictable bypassing, and its exposed memory hierarchy provides predictable latency. We demonstrate the effectiveness of this precision-timed (PRET) architecture through example applications running in simulation.

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Citation formats  
  • HTML
    Ben Lickly, Isaac Liu, Sungjun Kim, Hiren Patel, Stephen A.
    Edwards, Edward A. Lee. <a
    href="http://chess.eecs.berkeley.edu/pubs/475.html">Predictable
    Programming on a Precision Timed Architecture</a>,
    Proceedings of International Conference on Compilers,
    Architecture, and Synthesis from Embedded Systems (CASES),
    Atlanta, Georgia, Erik R. Altman (ed.), ACM, 137-146, 19,
    October, 2008; Published version available at <a
    href="http://portal.acm.org/citation.cfm?id=1450117"
    >ACM Portal</a>.
  • Plain text
    Ben Lickly, Isaac Liu, Sungjun Kim, Hiren Patel, Stephen A.
    Edwards, Edward A. Lee. "Predictable Programming on a
    Precision Timed Architecture". Proceedings of
    International Conference on Compilers, Architecture, and
    Synthesis from Embedded Systems (CASES), Atlanta, Georgia,
    Erik R. Altman (ed.), ACM, 137-146, 19, October, 2008;
    Published version available at <a
    href="http://portal.acm.org/citation.cfm?id=1450117"
    >ACM Portal</a>.
  • BibTeX
    @inproceedings{LicklyLiuKimPatelEdwardsLee08_PredictableProgrammingOnPrecisionTimedArchitecture,
        author = {Ben Lickly and Isaac Liu and Sungjun Kim and Hiren
                  Patel and Stephen A. Edwards and Edward A. Lee},
        title = {Predictable Programming on a Precision Timed
                  Architecture},
        booktitle = {Proceedings of International Conference on
                  Compilers, Architecture, and Synthesis from
                  Embedded Systems (CASES), Atlanta, Georgia},
        editor = {Erik R. Altman},
        organization = {ACM},
        pages = {137-146},
        day = {19},
        month = {October},
        year = {2008},
        note = {Published version available at <a
                  href="http://portal.acm.org/citation.cfm?id=1450117"
                  >ACM Portal</a>},
        abstract = {In a hard real-time embedded system, the time at
                  which a result is computed is as important as the
                  result itself. Modern processors go to extreme
                  lengths to ensure their function is predictable,
                  but have abandoned predictable timing in favor of
                  average-case performance. Real-time operating
                  systems provide timing-aware scheduling policies,
                  but without precise worst-case execution time
                  bounds they cannot provide guarantees. <br> We
                  describe an alternative in this paper: a
                  SPARC-based processor with predictable timing and
                  instruction-set extensions that provide precise
                  timing control. Its pipeline executes multiple,
                  independent hardware threads to avoid costly,
                  unpredictable bypassing, and its exposed memory
                  hierarchy provides predictable latency. We
                  demonstrate the effectiveness of this
                  precision-timed (PRET) architecture through
                  example applications running in simulation.},
        URL = {http://chess.eecs.berkeley.edu/pubs/475.html}
    }
    

Posted by Hiren Patel on 31 Jul 2008.
Groups: chess pret ptolemy
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