*banner
 

An Automated Mapping of Timed Functional Specification to A Precision Timed Architecture
Shanna-Shaye Forbes, Hugo Andrade, Hiren Patel, Edward A. Lee

Citation
Shanna-Shaye Forbes, Hugo Andrade, Hiren Patel, Edward A. Lee. "An Automated Mapping of Timed Functional Specification to A Precision Timed Architecture". Proceedings of the 12-th IEEE International Symposium on Distributed Simulation and Real Time Applications, October, 2008.

Abstract
Most common real-time embedded programming languages provide a means to specify functionality; however, they have few constructs to specify precise timing constraints. LabVIEW is one example of a graphical programming language that supports timing specifications in the form of timed-loops. In this work, we present a plug-in for LabVIEW Embedded that maps the LabVIEW G graphical programming language and its timing specifications to the PREcision Timed machine (PRET), an architecture that exposes timing instructions in its instruction set architecture. We demonstrate the use of the plug-in with a simple producer/consumer example that uses timing to enforce synchronization.

Electronic downloads

Citation formats  
  • HTML
    Shanna-Shaye Forbes, Hugo Andrade, Hiren Patel, Edward A.
    Lee. <a
    href="http://chess.eecs.berkeley.edu/pubs/482.html"
    >An Automated Mapping of Timed Functional Specification
    to A Precision Timed Architecture</a>, Proceedings of
    the 12-th IEEE International Symposium on Distributed
    Simulation and Real Time Applications, October, 2008.
  • Plain text
    Shanna-Shaye Forbes, Hugo Andrade, Hiren Patel, Edward A.
    Lee. "An Automated Mapping of Timed Functional
    Specification to A Precision Timed Architecture".
    Proceedings of the 12-th IEEE International Symposium on
    Distributed Simulation and Real Time Applications, October,
    2008.
  • BibTeX
    @inproceedings{ForbesAndradePatelLee08_AutomatedMappingOfTimedFunctionalSpecificationToPrecision,
        author = {Shanna-Shaye Forbes and Hugo Andrade and Hiren
                  Patel and Edward A. Lee},
        title = {An Automated Mapping of Timed Functional
                  Specification to A Precision Timed Architecture},
        booktitle = {Proceedings of the 12-th IEEE International
                  Symposium on Distributed Simulation and Real Time
                  Applications},
        month = {October},
        year = {2008},
        abstract = {Most common real-time embedded programming
                  languages provide a means to specify
                  functionality; however, they have few constructs
                  to specify precise timing constraints. LabVIEW is
                  one example of a graphical programming language
                  that supports timing specifications in the form of
                  timed-loops. In this work, we present a plug-in
                  for LabVIEW Embedded that maps the LabVIEW G
                  graphical programming language and its timing
                  specifications to the PREcision Timed machine
                  (PRET), an architecture that exposes timing
                  instructions in its instruction set architecture.
                  We demonstrate the use of the plug-in with a
                  simple producer/consumer example that uses timing
                  to enforce synchronization.},
        URL = {http://chess.eecs.berkeley.edu/pubs/482.html}
    }
    

Posted by Shanna-Shaye Forbes on 7 Aug 2008.
For additional information, see the Publications FAQ or contact webmaster at chess eecs berkeley edu.

Notice: This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright.

You are not logged in 
©2002-2014 Chess