*banner
 

Manycore Vector-Thread Architectures
Christopher Batten

Citation
Christopher Batten. "Manycore Vector-Thread Architectures". Talk or presentation, 10, March, 2009.

Abstract
Serious technology issues are breaking down the traditional abstractions in computer engineering. Power and energy consumption are now first-order design constraints and the road map for standard CMOS technology has never been more challenging. In response to these technology issues, computer architects are turning to multicore and manycore processors where tens to hundreds of cores are integrated on a single chip. However, this breaks down the traditional sequential execution abstraction forcing software programmers to parallelize their applications. This talk will introduce a new architectural approach called vector-threading (VT) which is a first step to addressing these challenges. Vector-threading combines the energy-efficiency and simple programming model of vector execution with the flexibility of multithreaded execution. This talk will also describe two implementations of vector-threading. The Scale VT Processor is a prototype for embedded applications implemented in a TSMC 0.18um process. Scale includes a RISC control processor and a four-lane vector-thread unit that can execute 16 operations per cycle and supports up to 128 active thraeds. The 16 sq mm chip runs at 260 MHz while consuming 0.4-1.1 W across a range of kernels. We have leveraged our insights from our first implementation of vector-threading to begin developing the Maven VT Processor. A Maven chip would include tens to hundreds of simple control processors each with its own single-lane vector-thread unit (VTU). A Maven single-lane VTU is potentially easier to implement and more efficient than a Scale multiple-lane VTU. Maven lanes can be coupled together with a combination of low-level software running on the control processor and fast hardware barriers.

Electronic downloads

Citation formats  
  • HTML
    Christopher Batten. <a
    href="http://chess.eecs.berkeley.edu/pubs/538.html"
    ><i>Manycore Vector-Thread
    Architectures</i></a>, Talk or presentation, 
    10, March, 2009.
  • Plain text
    Christopher Batten. "Manycore Vector-Thread
    Architectures". Talk or presentation,  10, March, 2009.
  • BibTeX
    @presentation{Batten09_ManycoreVectorThreadArchitectures,
        author = {Christopher Batten},
        title = {Manycore Vector-Thread Architectures},
        day = {10},
        month = {March},
        year = {2009},
        abstract = {Serious technology issues are breaking down the
                  traditional abstractions in computer engineering.
                  Power and energy consumption are now first-order
                  design constraints and the road map for standard
                  CMOS technology has never been more challenging.
                  In response to these technology issues, computer
                  architects are turning to multicore and manycore
                  processors where tens to hundreds of cores are
                  integrated on a single chip. However, this breaks
                  down the traditional sequential execution
                  abstraction forcing software programmers to
                  parallelize their applications. This talk will
                  introduce a new architectural approach called
                  vector-threading (VT) which is a first step to
                  addressing these challenges. Vector-threading
                  combines the energy-efficiency and simple
                  programming model of vector execution with the
                  flexibility of multithreaded execution. This talk
                  will also describe two implementations of
                  vector-threading. The Scale VT Processor is a
                  prototype for embedded applications implemented in
                  a TSMC 0.18um process. Scale includes a RISC
                  control processor and a four-lane vector-thread
                  unit that can execute 16 operations per cycle and
                  supports up to 128 active thraeds. The 16 sq mm
                  chip runs at 260 MHz while consuming 0.4-1.1 W
                  across a range of kernels. We have leveraged our
                  insights from our first implementation of
                  vector-threading to begin developing the Maven VT
                  Processor. A Maven chip would include tens to
                  hundreds of simple control processors each with
                  its own single-lane vector-thread unit (VTU). A
                  Maven single-lane VTU is potentially easier to
                  implement and more efficient than a Scale
                  multiple-lane VTU. Maven lanes can be coupled
                  together with a combination of low-level software
                  running on the control processor and fast hardware
                  barriers.},
        URL = {http://chess.eecs.berkeley.edu/pubs/538.html}
    }
    

Posted by Hiren Patel on 22 Mar 2009.
Groups: chess
For additional information, see the Publications FAQ or contact webmaster at chess eecs berkeley edu.

Notice: This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright.

You are not logged in 
©2002-2014 Chess