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Design as You See FIT: System-Level Soft Error Analysis of Sequential Circuits
Dan Holcomb

Citation
Dan Holcomb. "Design as You See FIT: System-Level Soft Error Analysis of Sequential Circuits". Talk or presentation, 31, March, 2009.

Abstract
Design as You See FIT: System-Level Soft Error Analysis of Sequential Circuits Abstract: Soft errors in combinational and sequential elements of dig- ital circuits are an increasing concern as a result of technol- ogy scaling. Several techniques exist for gate and latch harden- ing to synthesize circuits that are tolerant to soft errors. However, each such technique has associated overheads of power, area, and performance. In this work, we present a new methodology to compute the failures intime (FIT) rate of a sequential circuit where the failures are at the system-level. System-level failures are detected by monitors derived from functional specifcations. Our approach includes efficient methods to compute the FIT rate of combinational circuits (CFIT), incorporating effects of logical, timing, and electrical masking. The contribution of circuit components to the FIT rate of the overall circuit can be computed from the CFIT and probabilities of system-level failure due to soft errors in those elements. Designers can use this information to perform Pareto-optimal hardening of selected sequential and combinational components against soft errors. We present ex- perimental results demonstrating that our analysis is efficient, accurate, and provides data that can be used to synthesize a low-overhead, low-FIT sequential circuit.

Electronic downloads

Citation formats  
  • HTML
    Dan Holcomb. <a
    href="http://chess.eecs.berkeley.edu/pubs/580.html"
    ><i>Design as You See FIT: System-Level Soft Error
    Analysis of Sequential Circuits</i></a>, Talk or
    presentation,  31, March, 2009.
  • Plain text
    Dan Holcomb. "Design as You See FIT: System-Level Soft
    Error Analysis of Sequential Circuits". Talk or
    presentation,  31, March, 2009.
  • BibTeX
    @presentation{Holcomb09_DesignAsYouSeeFITSystemLevelSoftErrorAnalysisOfSequential,
        author = {Dan Holcomb},
        title = {Design as You See FIT: System-Level Soft Error
                  Analysis of Sequential Circuits},
        day = {31},
        month = {March},
        year = {2009},
        abstract = {Design as You See FIT: System-Level Soft Error
                  Analysis of Sequential Circuits Abstract: Soft
                  errors in combinational and sequential elements of
                  dig- ital circuits are an increasing concern as a
                  result of technol- ogy scaling. Several techniques
                  exist for gate and latch harden- ing to synthesize
                  circuits that are tolerant to soft errors.
                  However, each such technique has associated
                  overheads of power, area, and performance. In this
                  work, we present a new methodology to compute the
                  failures intime (FIT) rate of a sequential circuit
                  where the failures are at the system-level.
                  System-level failures are detected by monitors
                  derived from functional specifcations. Our
                  approach includes efficient methods to compute the
                  FIT rate of combinational circuits (CFIT),
                  incorporating effects of logical, timing, and
                  electrical masking. The contribution of circuit
                  components to the FIT rate of the overall circuit
                  can be computed from the CFIT and probabilities of
                  system-level failure due to soft errors in those
                  elements. Designers can use this information to
                  perform Pareto-optimal hardening of selected
                  sequential and combinational components against
                  soft errors. We present ex- perimental results
                  demonstrating that our analysis is efficient,
                  accurate, and provides data that can be used to
                  synthesize a low-overhead, low-FIT sequential
                  circuit. },
        URL = {http://chess.eecs.berkeley.edu/pubs/580.html}
    }
    

Posted by Hiren Patel on 27 Apr 2009.
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