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Design, Analysis, and Implementation of Static Dataflow Models for Hardware Targets
Kaushik Ravindran, Murali Parthasarathy

Citation
Kaushik Ravindran, Murali Parthasarathy. "Design, Analysis, and Implementation of Static Dataflow Models for Hardware Targets". Talk or presentation, 16, February, 2011; Presented at the Ninth Biennial Ptolemy Miniconference, Berkeley, CA.

Abstract
We present the DSP Designer framework to implement applications specified in the Static Dataflow (SDF) model of computation on hardware targets, such as FPGAs. Prior studies have shown the effectiveness of SDF as a natural model to specify multi-rate streaming applications. However, the focus of these works has primarily been on SDF implementations for processor targets. DSP Designer specializes the SDF model to make it suitable for hardware targets. It facilitates hardware actor definition and intellectual property (IP) integration. The back end additionally provides analysis methods tuned for synthesis of efficient hardware designs, such as resource allocation, memory optimization, and scheduler generation. The objective is to deliver an exploration framework that empowers application domain experts to become hardware designers. In this talk, we highlight key concepts underlying DSP Designer, demonstrate preliminary capabilities for exploration and implementation using practical applications, and discuss open challenges related to the specification of control and timing along with dataflow. We also summarize key features of the DSP Designer software architecture and invite partners to leverage our infrastructure and API to build tools for graphical design.

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  • HTML
    Kaushik Ravindran, Murali Parthasarathy. <a
    href="http://chess.eecs.berkeley.edu/pubs/813.html"><i>Design,
    Analysis, and Implementation of Static Dataflow Models for
    Hardware Targets</i></a>, Talk or presentation, 
    16, February, 2011; Presented at the <a
    href="http://ptolemy.eecs.berkeley.edu/conferences/11"
    >Ninth Biennial Ptolemy Miniconference</a>,
    Berkeley, CA.
  • Plain text
    Kaushik Ravindran, Murali Parthasarathy. "Design,
    Analysis, and Implementation of Static Dataflow Models for
    Hardware Targets". Talk or presentation,  16, February,
    2011; Presented at the <a
    href="http://ptolemy.eecs.berkeley.edu/conferences/11"
    >Ninth Biennial Ptolemy Miniconference</a>,
    Berkeley, CA.
  • BibTeX
    @presentation{RavindranParthasarathy11_DesignAnalysisImplementationOfStaticDataflowModels,
        author = {Kaushik Ravindran and Murali Parthasarathy},
        title = {Design, Analysis, and Implementation of Static
                  Dataflow Models for Hardware Targets},
        day = {16},
        month = {February},
        year = {2011},
        note = {Presented at the <a
                  href="http://ptolemy.eecs.berkeley.edu/conferences/11"
                  >Ninth Biennial Ptolemy Miniconference</a>,
                  Berkeley, CA.},
        abstract = {We present the DSP Designer framework to implement
                  applications specified in the Static Dataflow
                  (SDF) model of computation on hardware targets,
                  such as FPGAs. Prior studies have shown the
                  effectiveness of SDF as a natural model to specify
                  multi-rate streaming applications. However, the
                  focus of these works has primarily been on SDF
                  implementations for processor targets. DSP
                  Designer specializes the SDF model to make it
                  suitable for hardware targets. It facilitates
                  hardware actor definition and intellectual
                  property (IP) integration. The back end
                  additionally provides analysis methods tuned for
                  synthesis of efficient hardware designs, such as
                  resource allocation, memory optimization, and
                  scheduler generation. The objective is to deliver
                  an exploration framework that empowers application
                  domain experts to become hardware designers. In
                  this talk, we highlight key concepts underlying
                  DSP Designer, demonstrate preliminary capabilities
                  for exploration and implementation using practical
                  applications, and discuss open challenges related
                  to the specification of control and timing along
                  with dataflow. We also summarize key features of
                  the DSP Designer software architecture and invite
                  partners to leverage our infrastructure and API to
                  build tools for graphical design. },
        URL = {http://chess.eecs.berkeley.edu/pubs/813.html}
    }
    

Posted by Christopher Brooks on 18 Feb 2011.
Groups: ptolemy
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