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A Predictable and Command-Level Priority-Based DRAM Controller for Mixed-Criticality Systems
Hokeun Kim, David Broman, Edward A. Lee, Michael Zimmer, Aviral Shrivastava, Junkwang Oh

Citation
Hokeun Kim, David Broman, Edward A. Lee, Michael Zimmer, Aviral Shrivastava, Junkwang Oh. "A Predictable and Command-Level Priority-Based DRAM Controller for Mixed-Criticality Systems". Proceedings of the 21st IEEE Real-Time and Embedded Technology and Application Symposium (RTAS), Seattle, WA, USA, April, 2015.

Abstract
Mixed-criticality systems have tasks with different criticality levels running on the same hardware platform. Today's DRAM controllers cannot adequately satisfy the often conflicting requirements of tightly bounded worst-case latency for critical tasks and high performance for non-critical real-time tasks. We propose a DRAM memory controller that meets these requirements by using bank-aware address mapping and DRAM command-level priority-based scheduling with preemption. Many standard DRAM controllers can be extended with our approach, incurring no performance penalty when critical tasks are not generating DRAM requests. Our approach is evaluated by replaying memory traces obtained from executing benchmarks on an ARM ISA-based processor with caches, which is simulated on the gem5 architecture simulator. We compare our approach against previous TDM-based approaches, showing that our proposed memory controller achieves dramatically higher performance for non-critical tasks, without any significant impact on the worst- case latency of critical tasks.

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Citation formats  
  • HTML
    Hokeun Kim, David Broman, Edward A. Lee, Michael Zimmer,
    Aviral Shrivastava, Junkwang Oh. <a
    href="http://chess.eecs.berkeley.edu/pubs/1101.html"
    >A Predictable and Command-Level Priority-Based DRAM
    Controller for Mixed-Criticality Systems</a>,
    Proceedings of the 21st IEEE Real-Time and Embedded
    Technology and Application Symposium (RTAS), Seattle, WA,
    USA, April, 2015.
  • Plain text
    Hokeun Kim, David Broman, Edward A. Lee, Michael Zimmer,
    Aviral Shrivastava, Junkwang Oh. "A Predictable and
    Command-Level Priority-Based DRAM Controller for
    Mixed-Criticality Systems". Proceedings of the 21st
    IEEE Real-Time and Embedded Technology and Application
    Symposium (RTAS), Seattle, WA, USA, April, 2015.
  • BibTeX
    @inproceedings{KimBromanLeeZimmerShrivastavaOh15_PredictableCommandLevelPriorityBasedDRAMController,
        author = {Hokeun Kim and David Broman and Edward A. Lee and
                  Michael Zimmer and Aviral Shrivastava and Junkwang
                  Oh},
        title = {A Predictable and Command-Level Priority-Based
                  DRAM Controller for Mixed-Criticality Systems},
        booktitle = {Proceedings of the 21st IEEE Real-Time and
                  Embedded Technology and Application Symposium
                  (RTAS), Seattle, WA, USA},
        month = {April},
        year = {2015},
        abstract = {Mixed-criticality systems have tasks with
                  different criticality levels running on the same
                  hardware platform. Today's DRAM controllers cannot
                  adequately satisfy the often conflicting
                  requirements of tightly bounded worst-case latency
                  for critical tasks and high performance for
                  non-critical real-time tasks. We propose a DRAM
                  memory controller that meets these requirements by
                  using bank-aware address mapping and DRAM
                  command-level priority-based scheduling with
                  preemption. Many standard DRAM controllers can be
                  extended with our approach, incurring no
                  performance penalty when critical tasks are not
                  generating DRAM requests. Our approach is
                  evaluated by replaying memory traces obtained from
                  executing benchmarks on an ARM ISA-based processor
                  with caches, which is simulated on the gem5
                  architecture simulator. We compare our approach
                  against previous TDM-based approaches, showing
                  that our proposed memory controller achieves
                  dramatically higher performance for non-critical
                  tasks, without any significant impact on the
                  worst- case latency of critical tasks.},
        URL = {http://chess.eecs.berkeley.edu/pubs/1101.html}
    }
    

Posted by Hokeun Kim on 12 May 2015.
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