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Mapping a Timed Functional Specification to a Precision Timed (PRET) Machine
Shanna-Shaye Forbes, Hiren Patel, Hugo Andrade, Ben Lickly, Isaac Liu

Citation
Shanna-Shaye Forbes, Hiren Patel, Hugo Andrade, Ben Lickly, Isaac Liu. "Mapping a Timed Functional Specification to a Precision Timed (PRET) Machine". Talk or presentation, 21, February, 2008.

Abstract
Time sensitive tasks such as applying the break in an automobile, or switching tracks at a trail station have increased dependence on hard real-time embedded systems. For years a few programming languages have had the concept of timing, however embedded processors generally use best effort attempts to support timing and lack a direct correlation between timing specified in the programming language and direct support in the embedded architecture used. The PREcision Timed machine was created to guarantee the timing constraints specified in a programming language in the embedded architecture itself. This prompted a mapping from LabVIEW Embedded’s ‘G’ programming language which provides timing specifications to PRET which supports timing constraints. By modifying embedded x86 examples of LabVIEW’s generated C code we were able to successfully run initial experiments on PRET to determine attributes of the processors implementation which could be improved. The experiments pinpointed the need for determinism on PRET’s communication bus, as well as the need for timing analysis to determine the feasibility of multiple concurrent timed tasks without violating timing constraints. It also emphasizes the importance of automating the mapping between a programming language with timing constrains to the PRET processor. This poster presents ongoing research which explores mapping LabVIEW Embedded’s temporal specifications to a prototyped predictable and deterministic embedded processor known as the PREcision Timed Machine (PRET) [1]. [1] S. Edwards and E. A. Lee. The case for the precision timed (pret) machine. Technical Report No. UCB/EECS-2006-149, University of California, Berkeley 2006. [2] N. Instruments. Ni labview- the software that powers virtual instrumentation. http://www.ni.com/labview.

Electronic downloads

Citation formats  
  • HTML
    Shanna-Shaye Forbes, Hiren Patel, Hugo Andrade, Ben Lickly,
    Isaac Liu. <a
    href="http://chess.eecs.berkeley.edu/pubs/393.html"
    ><i>Mapping a Timed Functional Specification to a
    Precision Timed (PRET) Machine</i></a>, Talk or
    presentation,  21, February, 2008.
  • Plain text
    Shanna-Shaye Forbes, Hiren Patel, Hugo Andrade, Ben Lickly,
    Isaac Liu. "Mapping a Timed Functional Specification to
    a Precision Timed (PRET) Machine". Talk or
    presentation,  21, February, 2008.
  • BibTeX
    @presentation{ForbesPatelAndradeLicklyLiu08_MappingTimedFunctionalSpecificationToPrecisionTimedPRET,
        author = {Shanna-Shaye Forbes and Hiren Patel and Hugo
                  Andrade and Ben Lickly and Isaac Liu},
        title = {Mapping a Timed Functional Specification to a
                  Precision Timed (PRET) Machine},
        day = {21},
        month = {February},
        year = {2008},
        abstract = {Time sensitive tasks such as applying the break in
                  an automobile, or switching tracks at a trail
                  station have increased dependence on hard
                  real-time embedded systems. For years a few
                  programming languages have had the concept of
                  timing, however embedded processors generally use
                  best effort attempts to support timing and lack a
                  direct correlation between timing specified in the
                  programming language and direct support in the
                  embedded architecture used. The PREcision Timed
                  machine was created to guarantee the timing
                  constraints specified in a programming language in
                  the embedded architecture itself. This prompted a
                  mapping from LabVIEW Embeddedâs âGâ
                  programming language which provides timing
                  specifications to PRET which supports timing
                  constraints. By modifying embedded x86 examples of
                  LabVIEWâs generated C code we were able to
                  successfully run initial experiments on PRET to
                  determine attributes of the processors
                  implementation which could be improved. The
                  experiments pinpointed the need for determinism on
                  PRETâs communication bus, as well as the need
                  for timing analysis to determine the feasibility
                  of multiple concurrent timed tasks without
                  violating timing constraints. It also emphasizes
                  the importance of automating the mapping between a
                  programming language with timing constrains to the
                  PRET processor. This poster presents ongoing
                  research which explores mapping LabVIEW
                  Embeddedâs temporal specifications to a
                  prototyped predictable and deterministic embedded
                  processor known as the PREcision Timed Machine
                  (PRET) [1]. [1] S. Edwards and E. A. Lee. The case
                  for the precision timed (pret) machine. Technical
                  Report No. UCB/EECS-2006-149, University of
                  California, Berkeley 2006. [2] N. Instruments. Ni
                  labview- the software that powers virtual
                  instrumentation. http://www.ni.com/labview.},
        URL = {http://chess.eecs.berkeley.edu/pubs/393.html}
    }
    

Posted by Shanna-Shaye Forbes on 23 Feb 2008.
Groups: pret
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