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Predictable Programming on a Precision Timed Architecture
Hiren Patel

Citation
Hiren Patel. "Predictable Programming on a Precision Timed Architecture". Talk or presentation, 21, October, 2008.

Abstract
In a hard real-time embedded system the time at which a result is computed is as important as the result itself. Modern processors go to extreme lengths to ensure their function is predictable but have abandoned predictable timing in favor of average-case performance. Real-time operating systems provide timing-aware scheduling policies but without precise worst-case execution time bounds they cannot provide guarantees. We describe an alternative: a SPARC-based processor with predictable timing and instruction-set extensions that provide precise timing control. Its pipeline executes multiple independent hardware threads to avoid costly unpredictable bypassing and its exposed memory hierarchy provides predictable latency. We demonstrate the effectiveness of this precision-timed (PRET) architecture through example applications running in simulation.

Electronic downloads

Citation formats  
  • HTML
    Hiren Patel. <a
    href="http://chess.eecs.berkeley.edu/pubs/518.html"
    ><i>Predictable Programming on a Precision Timed
    Architecture</i></a>, Talk or presentation,  21,
    October, 2008.
  • Plain text
    Hiren Patel. "Predictable Programming on a Precision
    Timed Architecture". Talk or presentation,  21,
    October, 2008.
  • BibTeX
    @presentation{Patel08_PredictableProgrammingOnPrecisionTimedArchitecture,
        author = {Hiren Patel},
        title = {Predictable Programming on a Precision Timed
                  Architecture},
        day = {21},
        month = {October},
        year = {2008},
        abstract = {In a hard real-time em<x>bedded system the time at
                  which a result is computed is as important as the
                  result itself. Modern processors go to extreme
                  lengths to ensure their function is predictable
                  but have abandoned predictable timing in favor of
                  average-case performance. Real-time operating
                  systems provide timing-aware scheduling policies
                  but without precise worst-case execution time
                  bounds they cannot provide guarantees. We describe
                  an alternative: a SPARC-ba<x>sed processor with
                  predictable timing and instruction-set extensions
                  that provide precise timing control. Its pipeline
                  executes multiple independent hardware threads to
                  avoid costly unpredictable bypassing and its
                  exposed memory hierarchy provides predictable
                  latency. We demonstrate the effectiveness of this
                  precision-timed (PRET) architecture through
                  example applications running in simulation.},
        URL = {http://chess.eecs.berkeley.edu/pubs/518.html}
    }
    

Posted by Hiren Patel on 21 Jan 2009.
Groups: pret
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