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A Precision Timed Architecture for Timing Predictability and Repeatability
Hiren Patel, Isaac Liu, Ben Lickly, Edward A. Lee

Citation
Hiren Patel, Isaac Liu, Ben Lickly, Edward A. Lee. "A Precision Timed Architecture for Timing Predictability and Repeatability". Talk or presentation, 12, February, 2009.

Abstract
Most abstractions in computing hide timing properties of software. As a result, computer architects, and compiler and language designers use clever techniques to improve the average-case performance. This, however, is at the expense of predictable and repeatable timing. We find these techniques to be problematic for real-time embedded computing because they result in unpredictable and non-repeatable behavior, and brittle systems. Our approach treats time as a first-class property of embedded computing. In doing so, we prototype a precision timed (PRET) embedded processor architecture that introduces temporal semantics at the instruction-set architecture, and one that carefully selects architectural optimization techniques to deliver predictable performance enhancements. We believe that timing predictability and repeatability are not at odds with performance.

Electronic downloads

Citation formats  
  • HTML
    Hiren Patel, Isaac Liu, Ben Lickly, Edward A. Lee. <a
    href="http://chess.eecs.berkeley.edu/pubs/525.html"
    ><i>A Precision Timed Architecture for Timing
    Predictability and Repeatability</i></a>, Talk
    or presentation,  12, February, 2009.
  • Plain text
    Hiren Patel, Isaac Liu, Ben Lickly, Edward A. Lee. "A
    Precision Timed Architecture for Timing Predictability and
    Repeatability". Talk or presentation,  12, February,
    2009.
  • BibTeX
    @presentation{PatelLiuLicklyLee09_PrecisionTimedArchitectureForTimingPredictabilityRepeatability,
        author = {Hiren Patel and Isaac Liu and Ben Lickly and
                  Edward A. Lee},
        title = {A Precision Timed Architecture for Timing
                  Predictability and Repeatability},
        day = {12},
        month = {February},
        year = {2009},
        abstract = {Most abstractions in computing hide timing
                  properties of software. As a result, computer
                  architects, and compiler and language designers
                  use clever techniques to improve the average-case
                  performance. This, however, is at the expense of
                  predictable and repeatable timing. We find these
                  techniques to be problematic for real-time
                  embedded computing because they result in
                  unpredictable and non-repeatable behavior, and
                  brittle systems. Our approach treats time as a
                  first-class property of embedded computing. In
                  doing so, we prototype a precision timed (PRET)
                  embedded processor architecture that introduces
                  temporal semantics at the instruction-set
                  architecture, and one that carefully selects
                  architectural optimization techniques to deliver
                  predictable performance enhancements. We believe
                  that timing predictability and repeatability are
                  not at odds with performance. },
        URL = {http://chess.eecs.berkeley.edu/pubs/525.html}
    }
    

Posted by Hiren Patel on 11 Feb 2009.
Groups: chess pret
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