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A Disruptive Computer Design Idea: Architectures with Repeatable Timing
Stephen A. Edwards, Sungjun Kim, Edward A. Lee, Isaac Liu, Hiren Patel, Martin Schoeberl

Citation
Stephen A. Edwards, Sungjun Kim, Edward A. Lee, Isaac Liu, Hiren Patel, Martin Schoeberl. "A Disruptive Computer Design Idea: Architectures with Repeatable Timing". Proceedings of IEEE International Conference on Computer Design (ICCD), IEEE, 4, October, 2009; Lake Tahoe, CA.

Abstract
This paper argues that repeatable timing is more important and more achievable than predictable timing. It describes microarchitecture approaches to pipelining and memory hierarchy that deliver repeatable timing and promise comparable or better performance compared to established techniques. Specifically, threads are interleaved in a pipeline to eliminate pipeline hazards, and a hierarchical memory architecture is outlined that hides memory latencies.

Electronic downloads

Citation formats  
  • HTML
    Stephen A. Edwards, Sungjun Kim, Edward A. Lee, Isaac Liu,
    Hiren Patel, Martin Schoeberl. <a
    href="http://chess.eecs.berkeley.edu/pubs/614.html"
    >A Disruptive Computer Design Idea: Architectures with
    Repeatable Timing</a>, Proceedings of IEEE
    International Conference on Computer Design (ICCD), IEEE, 4,
    October, 2009; Lake Tahoe, CA.
  • Plain text
    Stephen A. Edwards, Sungjun Kim, Edward A. Lee, Isaac Liu,
    Hiren Patel, Martin Schoeberl. "A Disruptive Computer
    Design Idea: Architectures with Repeatable Timing".
    Proceedings of IEEE International Conference on Computer
    Design (ICCD), IEEE, 4, October, 2009; Lake Tahoe, CA.
  • BibTeX
    @inproceedings{EdwardsKimLeeLiuPatelSchoeberl09_DisruptiveComputerDesignIdeaArchitecturesWithRepeatable,
        author = {Stephen A. Edwards and Sungjun Kim and Edward A.
                  Lee and Isaac Liu and Hiren Patel and Martin
                  Schoeberl},
        title = {A Disruptive Computer Design Idea: Architectures
                  with Repeatable Timing},
        booktitle = {Proceedings of IEEE International Conference on
                  Computer Design (ICCD)},
        organization = {IEEE},
        day = {4},
        month = {October},
        year = {2009},
        note = {Lake Tahoe, CA},
        abstract = {This paper argues that repeatable timing is more
                  important and more achievable than predictable
                  timing. It describes microarchitecture approaches
                  to pipelining and memory hierarchy that deliver
                  repeatable timing and promise comparable or better
                  performance compared to established techniques.
                  Specifically, threads are interleaved in a
                  pipeline to eliminate pipeline hazards, and a
                  hierarchical memory architecture is outlined that
                  hides memory latencies.},
        URL = {http://chess.eecs.berkeley.edu/pubs/614.html}
    }
    

Posted by Edward A. Lee on 25 Aug 2009.
Groups: ptolemy
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