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From Formal Verification to Synthesis
Rajeev Alur

Citation
Rajeev Alur. "From Formal Verification to Synthesis". Talk or presentation, 18, August, 2010; Presented at the Strategic Directions in Software at Scale (SaS), Berkeley, CA. .

Abstract
(No abstract.)

Electronic downloads

  • Alur.pdf · application/pdf · 500 kbytes
Citation formats  
  • HTML
    Rajeev Alur. <a
    href="http://chess.eecs.berkeley.edu/pubs/687.html"
    ><i>From Formal Verification to
    Synthesis</i></a>, Talk or presentation,  18,
    August, 2010; Presented at the <a
    href="http://chess.eecs.berkeley.edu/conferences/10/SDISAS/index.htm">Strategic
    Directions in Software at Scale (SaS)</a>, Berkeley,
    CA.
    .
  • Plain text
    Rajeev Alur. "From Formal Verification to
    Synthesis". Talk or presentation,  18, August, 2010;
    Presented at the <a
    href="http://chess.eecs.berkeley.edu/conferences/10/SDISAS/index.htm">Strategic
    Directions in Software at Scale (SaS)</a>, Berkeley,
    CA.
    .
  • BibTeX
    @presentation{Alur10_FromFormalVerificationToSynthesis,
        author = {Rajeev Alur},
        title = {From Formal Verification to Synthesis},
        day = {18},
        month = {August},
        year = {2010},
        note = {Presented at the <a
                  href="http://chess.eecs.berkeley.edu/conferences/10/SDISAS/index.htm">Strategic
                  Directions in Software at Scale (SaS)</a>,
                  Berkeley, CA.
    },
        abstract = {(No abstract.)},
        URL = {http://chess.eecs.berkeley.edu/pubs/687.html}
    }
    

Posted by Mary Stewart on 24 Aug 2010.
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