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VHDL Code Generation in the Ptolemy II Environment
Jackie Man-Kit Leung, Terry Filiba, Vinayak Nagpal

Citation
Jackie Man-Kit Leung, Terry Filiba, Vinayak Nagpal. "VHDL Code Generation in the Ptolemy II Environment". Technical report, EECS Department, University of California, Berkeley, UCB/EECS-2008-140, October, 2008.

Abstract
It is becoming increasingly popular to describe real time signal processing systems targeted for FPGA or ASIC implementation using structural signal flow graphs. We have implemented support for generation of synthesizeable as well as testbench VHDL code from Ptolemy II models. A helper based approach borrowing heavily from the existing Ptolemy II C code generation framework is used. This work demonstrates the extensibility of the helper based code generation approach and sets the stage for future research in synthesis of efficient hardware descriptions from heterogenous visual models.

Electronic downloads

Citation formats  
  • HTML
    Jackie Man-Kit Leung, Terry Filiba, Vinayak Nagpal. <a
    href="http://chess.eecs.berkeley.edu/pubs/778.html"
    ><i>VHDL Code Generation in the Ptolemy II
    Environment</i></a>, Technical report,  EECS
    Department, University of California, Berkeley,
    UCB/EECS-2008-140, October, 2008.
  • Plain text
    Jackie Man-Kit Leung, Terry Filiba, Vinayak Nagpal.
    "VHDL Code Generation in the Ptolemy II
    Environment". Technical report,  EECS Department,
    University of California, Berkeley, UCB/EECS-2008-140,
    October, 2008.
  • BibTeX
    @techreport{LeungFilibaNagpal08_VHDLCodeGenerationInPtolemyIIEnvironment,
        author = {Jackie Man-Kit Leung and Terry Filiba and Vinayak
                  Nagpal},
        title = {VHDL Code Generation in the Ptolemy II Environment},
        institution = {EECS Department, University of California, Berkeley},
        number = {UCB/EECS-2008-140},
        month = {October},
        year = {2008},
        abstract = {It is becoming increasingly popular to describe
                  real time signal processing systems targeted for
                  FPGA or ASIC implementation using structural
                  signal flow graphs. We have implemented support
                  for generation of synthesizeable as well as
                  testbench VHDL code from Ptolemy II models. A
                  helper based approach borrowing heavily from the
                  existing Ptolemy II C code generation framework is
                  used. This work demonstrates the extensibility of
                  the helper based code generation approach and sets
                  the stage for future research in synthesis of
                  efficient hardware descriptions from heterogenous
                  visual models.},
        URL = {http://chess.eecs.berkeley.edu/pubs/778.html}
    }
    

Posted by Christopher Brooks on 13 Nov 2010.
Groups: ptolemy
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