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A PRET Architecture Supporting Concurrent Programs with Composable Timing Properties
Isaac Liu, Jan Reineke, Edward A. Lee

Citation
Isaac Liu, Jan Reineke, Edward A. Lee. "A PRET Architecture Supporting Concurrent Programs with Composable Timing Properties". 44th Asilomar Conference on Signals, Systems, and Computers, 2111-2115, 7, November, 2010.

Abstract
In order to improve design time and efficiency of systems, large scale system design is often split into the design of separate functions, which are later integrated together. For real time safety critical applications, the ability to separately verify timing properties of functions is important. If the integration of functions on a particular platform destroys the timing properties of individual functions, then it is not possible to verify timing properties separately. Modern computer architectures introduce timing interference between functions due to unrestricted access of shared hardware resources, such as pipelines and caches. Thus, it is difficult, if not impossible, to integrate two functions on a modern computer architecture while preserving their separate timing properties. This paper describes a realization of PRET, a class of computer architectures designed for timing predictability. Our realization employs a thread-interleaved pipeline with scratchpad memories, and has a predictable DRAM controller. It decouples execution of multiple hardware contexts on a shared hardware platform, which allows for a straight forward integration of different functions onto a shared platform.

Electronic downloads

Citation formats  
  • HTML
    Isaac Liu, Jan Reineke, Edward A. Lee. <a
    href="http://chess.eecs.berkeley.edu/pubs/803.html"
    >A PRET Architecture Supporting Concurrent  Programs with
    Composable Timing Properties</a>, 44th Asilomar
    Conference  on Signals, Systems, and Computers, 2111-2115,
    7, November, 2010.
  • Plain text
    Isaac Liu, Jan Reineke, Edward A. Lee. "A PRET
    Architecture Supporting Concurrent  Programs with Composable
    Timing Properties". 44th Asilomar Conference  on
    Signals, Systems, and Computers, 2111-2115, 7, November,
    2010.
  • BibTeX
    @inproceedings{LiuReinekeLee10_PRETArchitectureSupportingConcurrentProgramsWithComposable,
        author = {Isaac Liu and Jan Reineke and Edward A. Lee},
        title = {A PRET Architecture Supporting Concurrent 
                  Programs with Composable Timing Properties},
        booktitle = {44th Asilomar Conference  on Signals, Systems, and
                  Computers},
        pages = {2111-2115},
        day = {7},
        month = {November},
        year = {2010},
        abstract = {In order to improve design time and efficiency of
                  systems, large scale system design is often split
                  into the design of separate functions, which are
                  later integrated together. For real time safety
                  critical applications, the ability to separately
                  verify timing properties of functions is
                  important. If the integration of functions on a
                  particular platform destroys the timing properties
                  of individual functions, then it is not possible
                  to verify timing properties separately. Modern
                  computer architectures introduce timing
                  interference between functions due to unrestricted
                  access of shared hardware resources, such as
                  pipelines and caches. Thus, it is difficult, if
                  not impossible, to integrate two functions on a
                  modern computer architecture while preserving
                  their separate timing properties. This paper
                  describes a realization of PRET, a class of
                  computer architectures designed for timing
                  predictability. Our realization employs a
                  thread-interleaved pipeline with scratchpad
                  memories, and has a predictable DRAM controller.
                  It decouples execution of multiple hardware
                  contexts on a shared hardware platform, which
                  allows for a straight forward integration of
                  different functions onto a shared platform.},
        URL = {http://chess.eecs.berkeley.edu/pubs/803.html}
    }
    

Posted by Jan Reineke on 6 Feb 2011.
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