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Automated Bit-Width Analysis Using Ptolemy
Mike Wirthlin

Citation
Mike Wirthlin. "Automated Bit-Width Analysis Using Ptolemy". Talk or presentation, 16, February, 2011; Poster presented at the Ninth Biennial Ptolemy Miniconference, Berkeley, CA.

Abstract
When using general purpose hardware such as DSPs and CPUs, a single system bit width is simple and usually sufficient to meet the quantization error requirements of the system. However, when creating custom DSP hardware in an FPGA or ASIC, a single system bit width is inefficient and consumes more area than necessary. One way of improving the efficiency of custom hardware signal processing systems is to customize the bit-width of each operator in the system. Significant hardware savings are possible while still meeting a quantization error constraint through bit-width optimization. Unfortunately, finding an optimal set of minimum bit widths has been show to be NP complete. Many papers have explored heuristics for finding a set of minimum bit-widths in a reasonable time. Many involve propagating ranges through a system to find the range of both the magnitude of the output and the quantization error. While many techniques for bit-width optimization have been published, few of these techniques are readily available to DSP engineers. This project created a bit-width analysis framework within Ptolemy to facilitate the bit-width optimization of DSP systems. Several published techniques for bit-width optimization were implemented within Ptolemy by creating a new director and a set of new tokens. A custom director was created to organize and schedule the bit-width selection algorithm. A set of range tokens was added to find and propagate ranges of signals throughout the system. The system was also designed to allow the easy addition of new techniques as they are published. The benefit of bit-width analysis is demonstrated with several DSP models.

Electronic downloads

Citation formats  
  • HTML
    Mike Wirthlin. <a
    href="http://chess.eecs.berkeley.edu/pubs/831.html"><i>Automated
    Bit-Width Analysis Using Ptolemy</i></a>, Talk
    or presentation,  16, February, 2011; Poster presented at
    the <a
    href="http://ptolemy.eecs.berkeley.edu/conferences/11"
    >Ninth Biennial Ptolemy Miniconference</a>,
    Berkeley, CA.
  • Plain text
    Mike Wirthlin. "Automated Bit-Width Analysis Using
    Ptolemy". Talk or presentation,  16, February, 2011;
    Poster presented at the <a
    href="http://ptolemy.eecs.berkeley.edu/conferences/11"
    >Ninth Biennial Ptolemy Miniconference</a>,
    Berkeley, CA.
  • BibTeX
    @presentation{Wirthlin11_AutomatedBitWidthAnalysisUsingPtolemy,
        author = {Mike Wirthlin},
        title = {Automated Bit-Width Analysis Using Ptolemy},
        day = {16},
        month = {February},
        year = {2011},
        note = {Poster presented at the <a
                  href="http://ptolemy.eecs.berkeley.edu/conferences/11"
                  >Ninth Biennial Ptolemy Miniconference</a>,
                  Berkeley, CA.},
        abstract = {When using general purpose hardware such as DSPs
                  and CPUs, a single system bit width is simple and
                  usually sufficient to meet the quantization error
                  requirements of the system. However, when creating
                  custom DSP hardware in an FPGA or ASIC, a single
                  system bit width is inefficient and consumes more
                  area than necessary. One way of improving the
                  efficiency of custom hardware signal processing
                  systems is to customize the bit-width of each
                  operator in the system. Significant hardware
                  savings are possible while still meeting a
                  quantization error constraint through bit-width
                  optimization. Unfortunately, finding an optimal
                  set of minimum bit widths has been show to be NP
                  complete. Many papers have explored heuristics for
                  finding a set of minimum bit-widths in a
                  reasonable time. Many involve propagating ranges
                  through a system to find the range of both the
                  magnitude of the output and the quantization
                  error. While many techniques for bit-width
                  optimization have been published, few of these
                  techniques are readily available to DSP engineers.
                  This project created a bit-width analysis
                  framework within Ptolemy to facilitate the
                  bit-width optimization of DSP systems. Several
                  published techniques for bit-width optimization
                  were implemented within Ptolemy by creating a new
                  director and a set of new tokens. A custom
                  director was created to organize and schedule the
                  bit-width selection algorithm. A set of range
                  tokens was added to find and propagate ranges of
                  signals throughout the system. The system was also
                  designed to allow the easy addition of new
                  techniques as they are published. The benefit of
                  bit-width analysis is demonstrated with several
                  DSP models. },
        URL = {http://chess.eecs.berkeley.edu/pubs/831.html}
    }
    

Posted by Christopher Brooks on 18 Feb 2011.
Groups: ptolemy
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