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PRET DRAM Controller: Bank Privatization for Predictability and Temporal Isolation
Jan Reineke, Isaac Liu, Hiren Patel, Sungjun Kim, Edward A. Lee

Citation
Jan Reineke, Isaac Liu, Hiren Patel, Sungjun Kim, Edward A. Lee. "PRET DRAM Controller: Bank Privatization for Predictability and Temporal Isolation". CODES+ISSS '11: Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, ACM, 99-108, October, 2011.

Abstract
Hard real-time embedded systems employ high-capacity memories such as Dynamic RAMs (DRAMs) to cope with increasing data and code sizes of modern designs. However, memory controller design has so far largely focused on improving average-case performance. As a consequence, the latency of memory accesses is unpredictable, which complicates the worst-case execution time analysis necessary for hard real-time embedded systems. Our work introduces a novel DRAM controller design that is predictable and that significantly reduces worst-case access latencies. Instead of viewing the DRAM device as one resource that can only be shared as a whole, our approach views it as multiple resources that can be shared between one or more clients individually. We partition the physical address space following the internal structure of the DRAM device, i.e., its ranks and banks, and interleave accesses to the blocks of this partition. This eliminates contention for shared resources within the device, making accesses temporally predictable and temporally isolated. This paper describes our DRAM controller design and its integration with a precision-timed (PRET) architecture called PTARM. We present analytical bounds on the latency and throughput of the proposed controller, and confirm these via simulation.

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Citation formats  
  • HTML
    Jan Reineke, Isaac Liu, Hiren Patel, Sungjun Kim, Edward A.
    Lee. <a
    href="http://chess.eecs.berkeley.edu/pubs/851.html"
    >PRET DRAM Controller: Bank Privatization for
    Predictability and Temporal Isolation</a>, CODES+ISSS
    '11: Proceedings of the seventh IEEE/ACM/IFIP international
    conference on Hardware/software codesign and system
    synthesis, ACM, 99-108, October, 2011.
  • Plain text
    Jan Reineke, Isaac Liu, Hiren Patel, Sungjun Kim, Edward A.
    Lee. "PRET DRAM Controller: Bank Privatization for
    Predictability and Temporal Isolation". CODES+ISSS '11:
    Proceedings of the seventh IEEE/ACM/IFIP international
    conference on Hardware/software codesign and system
    synthesis, ACM, 99-108, October, 2011.
  • BibTeX
    @inproceedings{ReinekeLiuPatelKimLee11_PRETDRAMControllerBankPrivatizationForPredictability,
        author = {Jan Reineke and Isaac Liu and Hiren Patel and
                  Sungjun Kim and Edward A. Lee},
        title = {PRET DRAM Controller: Bank Privatization for
                  Predictability and Temporal Isolation},
        booktitle = {CODES+ISSS '11: Proceedings of the seventh
                  IEEE/ACM/IFIP international conference on
                  Hardware/software codesign and system synthesis},
        organization = {ACM},
        pages = {99-108},
        month = {October},
        year = {2011},
        abstract = {Hard real-time embedded systems employ
                  high-capacity memories such as Dynamic RAMs
                  (DRAMs) to cope with increasing data and code
                  sizes of modern designs. However, memory
                  controller design has so far largely focused on
                  improving average-case performance. As a
                  consequence, the latency of memory accesses is
                  unpredictable, which complicates the worst-case
                  execution time analysis necessary for hard
                  real-time embedded systems. Our work introduces a
                  novel DRAM controller design that is predictable
                  and that significantly reduces worst-case access
                  latencies. Instead of viewing the DRAM device as
                  one resource that can only be shared as a whole,
                  our approach views it as multiple resources that
                  can be shared between one or more clients
                  individually. We partition the physical address
                  space following the internal structure of the DRAM
                  device, i.e., its ranks and banks, and interleave
                  accesses to the blocks of this partition. This
                  eliminates contention for shared resources within
                  the device, making accesses temporally predictable
                  and temporally isolated. This paper describes our
                  DRAM controller design and its integration with a
                  precision-timed (PRET) architecture called PTARM.
                  We present analytical bounds on the latency and
                  throughput of the proposed controller, and confirm
                  these via simulation.},
        URL = {http://chess.eecs.berkeley.edu/pubs/851.html}
    }
    

Posted by Jan Reineke on 7 Aug 2011.
Groups: pret
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