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Time-predictable and composable architectures for dependable embedded systems
Saddek Bensalem, Kees Goossens, Christoph M. Kirsch, Roman Obermaisser, Edward A. Lee, Joseph Sifakis

Citation
Saddek Bensalem, Kees Goossens, Christoph M. Kirsch, Roman Obermaisser, Edward A. Lee, Joseph Sifakis. "Time-predictable and composable architectures for dependable embedded systems". Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis (CODES+ISSS '11), ACM, 351-352, October, 2011.

Abstract
Current hardware design practice often relies on integration of components, some of which may be IP or legacy blocks. While integration eases design by allowing modularization and component reuse, it is still done in a mostly ad hoc manner. Designers work with descriptions of components that are either informal or incomplete (e.g., documents in English, structural but non-behavioral specifications in IP-XACT) or too low-level (e.g., HDL code), and have little to no automatic support for stitching the components together. Providing such support is the glue design problem.

This paper addresses this problem using a model-based approach. The key idea is to use high-level models, such as dataflow graphs, that enable efficient automated analysis. The analysis can be used to derive performance properties of the system (e.g., component compatibility, throughput, etc.), optimize resource usage (e.g., buffer sizes), and even synthesize low-level code (e.g., control logic). However, these models are only abstractions of the real system, and often omit critical information. As a result, the analysis outcomes may be defensive (e.g., buffers that are too big) or even incorrect (e.g., buffers that are too small). The paper examines these situations and proposes a correct and non-defensive design methodology that employs the right models to explore accurate performance and resource trade-offs.

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Citation formats  
  • HTML
    Saddek Bensalem, Kees Goossens, Christoph M. Kirsch, Roman
    Obermaisser, Edward A. Lee, Joseph Sifakis. <a
    href="http://chess.eecs.berkeley.edu/pubs/884.html"
    >Time-predictable and composable architectures for
    dependable embedded systems</a>, Proceedings of the
    seventh IEEE/ACM/IFIP international conference on
    Hardware/software codesign and system synthesis (CODES+ISSS
    '11), ACM, 351-352, October, 2011.
  • Plain text
    Saddek Bensalem, Kees Goossens, Christoph M. Kirsch, Roman
    Obermaisser, Edward A. Lee, Joseph Sifakis.
    "Time-predictable and composable architectures for
    dependable embedded systems". Proceedings of the
    seventh IEEE/ACM/IFIP international conference on
    Hardware/software codesign and system synthesis (CODES+ISSS
    '11), ACM, 351-352, October, 2011.
  • BibTeX
    @inproceedings{BensalemGoossensKirschObermaisserLeeSifakis11_TimepredictableComposableArchitecturesForDependable,
        author = {Saddek Bensalem and Kees Goossens and Christoph M.
                  Kirsch and Roman Obermaisser and Edward A. Lee and
                  Joseph Sifakis},
        title = {Time-predictable and composable architectures for
                  dependable embedded systems},
        booktitle = {Proceedings of the seventh IEEE/ACM/IFIP
                  international conference on Hardware/software
                  codesign and system synthesis (CODES+ISSS '11)},
        organization = {ACM},
        pages = {351-352},
        month = {October},
        year = {2011},
        abstract = {Current hardware design practice often relies on
                  integration of components, some of which may be IP
                  or legacy blocks. While integration eases design
                  by allowing modularization and component reuse, it
                  is still done in a mostly ad hoc manner. Designers
                  work with descriptions of components that are
                  either informal or incomplete (e.g., documents in
                  English, structural but non-behavioral
                  specifications in IP-XACT) or too low-level (e.g.,
                  HDL code), and have little to no automatic support
                  for stitching the components together. Providing
                  such support is the glue design problem. <p>This
                  paper addresses this problem using a model-based
                  approach. The key idea is to use high-level
                  models, such as dataflow graphs, that enable
                  efficient automated analysis. The analysis can be
                  used to derive performance properties of the
                  system (e.g., component compatibility, throughput,
                  etc.), optimize resource usage (e.g., buffer
                  sizes), and even synthesize low-level code (e.g.,
                  control logic). However, these models are only
                  abstractions of the real system, and often omit
                  critical information. As a result, the analysis
                  outcomes may be defensive (e.g., buffers that are
                  too big) or even incorrect (e.g., buffers that are
                  too small). The paper examines these situations
                  and proposes a correct and non-defensive design
                  methodology that employs the right models to
                  explore accurate performance and resource
                  trade-offs.},
        URL = {http://chess.eecs.berkeley.edu/pubs/884.html}
    }
    

Posted by Christopher Brooks on 10 Jan 2012.
Groups: ptolemy
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